The computers and methods disclosed herein relate to hypervisor-controlled virtualization and, more particularly, to computers and methods that employ a mechanism for eliminating a race condition between a hypervisor-performed emulation process requiring a translation operation using one or more different types of translation tables (e.g., page tables and, if applicable, segment tables), and a concurrent translation table entry invalidation.
Virtualization refers to a state where multiple operating systems, including hypervisor and one or more guest operating systems, are concurrently executed by one or more processor(s) on the same computer, referred to herein as a host machine. A hypervisor is a host operating system that supports such virtualization. Specifically, the hypervisor controls execution of the guest operating system(s) by the processor(s) of the host machine in order to ensure that the guest operating system(s) can function without disruption.
With such virtualization, there are many scenarios in which the hypervisor must emulate instructions for a given guest operating system. Such instructions can include, for example, instructions that require access to data stored in memory (referred to herein as storage access instructions). To emulate a storage access instruction, the hypervisor typically manually translates (in software) a virtual address associated with the instruction into a physical address. To do this, the hypervisor performs a page table walk (also referred to herein as a page table search), during which one or more page tables are searched using a virtual address associated with the storage access instruction as a search key in order to acquire an actual physical address. Those skilled in the art will recognize that, depending upon the type of memory management being used, the virtual address may be specified in the storage access instruction or, alternatively, an effective address may be specified. If an effective address is specified, the hypervisor must first manually translate (in software) the effective address into the virtual address by performing a segment table walk (also referred to herein as a segment table search), during which one or more segment tables are searched using the effective address associated with the storage access instruction as a search key in order to acquire the virtual address. In any case, once the virtual address is acquired, it can be translated into the actual physical address, as discussed above. For purposes of this disclosure, it should be understood that page tables and segment tables are different types of “translation tables”. Once the actual physical address is acquired, the hypervisor can access the physical address and complete the instruction, thereby completing the emulation process.
However, from the time this emulation process begins until the time that it is completed (i.e., until the physical address is accessed and the instruction is completed), there is a possibility that a required translation table entry (e.g., a required page table entry or, if applicable, a required segment table entry) used for the translation could be invalidated by any one of the multiple operating systems such that the physical address acquired and used to complete the instruction is no longer accurate. The condition of having to complete an emulation process before an invalidation of a required translation table entry is referred to herein as a race condition and, because the inability to complete the emulation process before translation table entry invalidation occurs can disrupt guest operating system operations, there is a need in the art for a mechanism that eliminates such race conditions.